This invention relates generally to semiconductor memory systems and, more specifically, to semiconductor memory systems employing random access memory devices which have both volatile and nonvolatile binary data storage capability and which require write and erase voltages of opposite polarity at a magnitude greater than that of the power supply voltage otherwise required to operate the system.
Semiconductor random access memory (RAM) systems generally fall into two categories: static RAM systems and dynamic RAM systems. Static RAM systems typically employ bistable multivibrators or flip-flops with the stored bit value determined by which of the two bistable states the multivibrator is in. Dynamic RAMs typically employ a cell arrangement with the stored bit value determined by the presence or absence of a voltage stored on a semiconductor capacitor structure. Since static RAMs employ bistable devices, the bit content of each cell is retained without refreshing and the readout of the bit content is nondestructive. Dynamic RAMs on the other hand typically require periodic refreshing of the information stored on the capacitor although the readout may be either destructive or nondestructive depending on the cell design. Semiconductor RAMs are generally volatile devices, i.e., the bit content of the memory is typically lost if electric power to the RAM is removed or lost. However, over the past decade or so various approaches have been taken to adding backup nonvolatile storage capability to otherwise volatile RAMs. These RAMs will herein be referred to as volatile/nonvolatile RAMs or simply V/NV RAMs.
In general static RAM cells can be provided with nonvolatile backup data storage capability by adding nonvolatile, threshold-alterable devices of the transistor or capacitor variety to the typical RAM cell. Static V/NV RAM cells incorporating nonvolatile transistors are disclosed in the following exemplary references: Mark et al. U.S. Pat. No. 3,636,530; Lockwood U.S. Pat. No. 3,676,717; an article by Frohman-Bentchkowsky, entitled "The Metal-Nitride-Oxide-Silicon (MNOS) Transistor--Characteristics and Applications", PROCEEDINGS OF THE IEEE, Vol. 58, No. 8, August 1970 (page 1218); Uchida et al. U.S. Pat. No. 3,950,737; and Uchida U.S. Pat. No. 4,044,343. Flip-flop cells employing nonvolatile transistor backup devices have been employed in nonvolatile counter circuits manufactured by various companies for electronic artillery fuse applications and for other general purpose uses. They are also employed in several static V/NV RAM integrated circuits (ICs) commercially available from several companies. Static V/NV RAM cells using nonvolatile capacitor elements are disclosed in the following exemplary prior art references: Ho et al U.S. Pat. No. 3,662,351, and Schuermeyer et al. U.S. Pat. No. 4,091,460.
Dynamic V/NV RAM cells employing nonvolatile semiconductor storage devices are shown in the following exemplary references: Aneshansley U.S. Pat. No. 3,761,901; Aneshansley U.S. Pat. No. 3,771,148; Shaffer U.S. Pat. No. 3,774,177; and Schaffer U.S. Pat. No. 3,922,650. A dynamic V/NV RAM system employing nonvolatile devices is also shown in a copending application of Wendell Spence, now issued as U.S. Pat. No. 4,175,291.
Implementation of any of these V/NV static and dynamic RAM systems utilizing five volt, n-channel, silicon-insulator-silicon (SIS) device technology still requires that opposite polarity write and erase voltages having a magnitude of about twenty or twenty-five volts be supplied to the RAMs for writing and erasing information in the nonvolatile storage devices. In the past these opposite polarity write and erase voltages have been supplied either from a DC power supply system capable of providing twenty-five volt signals of both polarities or by employing a single relatively high voltage power supply and providing a circuit for inverting the power supply voltage to an opposite polarity voltage. With the thrust of semiconductor technology strongly in the direction of five volt, n-channel, SIS device technology, it is highly disadvantageous to require a relatively high voltage power supply to be used in the system solely to supply the voltage magnitude requirements for writing and erasing nonvolatile memory components. The manufacturing and operating cost of such power supplies is considerably greater than a single five volt power supply and, accordingly, it would be useful to be able to provide the write and erase voltages required for V/NV memory components from a single five volt power supply.